Free · Strategic silicon digital synthesized
Joule M5 base SoC
Monolithic RISC-V SoC for the Joule SiP ecosystem — VexRiscv + seL4 + Rust, 384KB SRAM, ReRAM, GPIF→CrossLink-NX bridge. Designed for SKY130 with OpenFrame pinout.
Process targets
- · sky130
License
Apache-2.0
Origin: internal · open-source
Faux-moat bypassed
A complete RISC-V SoC pre-wired for the chipIgnite OpenFrame pinout is not in any public catalog. Customers either start from raw Caravel template or pay vendors for commercial SoC IP.
Value to customer
Drop-in base SoC for any sky130 design that needs a CPU + memory + bus. Use as the digital host for analog/sensor/photonic chiplets in a SiP.
Periodic Stack primitives
risc-v-coresram-bankrerom-bridgewishbone-bus
last curated: 2026-06-05 status: catalog-ready