Open AI server node
The apex system — where the host is all reuse, and the value and the joules live in two places.
Grand Teton is an open AI platform: dual-socket host, eight accelerators on a baseboard, 48 V power. OCP standardised the entire host. What is left to design is exactly the value — the accelerator silicon and the wires between accelerators — and both are an energy problem.
Exploded
Decompose the product into its stack. Each layer is colour-coded by what it is to the next build.
Bill of materials
Every part is a real, sourced component from the open baseline — no invented part numbers.
The value and the joules. openWafer’s slice is both the compute die and co-packaged optical I/O — so bits move between chips in light, not copper, where a moved bit costs the fewest joules. That optical interconnect is the photonic tile from the frontier build, dropped into the rack.
https://www.opencompute.org/documents/ocp-accelerator-module-design-specification-v1p5-final-20220223-docx-1-pdf →Standard server CPU — refreshes on a node clock. Reuse the current generation.
https://www.opencompute.org/documents/grand-teton-intel-based-cpu-tray-specification-v1-0-pdf →Standard DIMMs. Reuse the current generation.
https://www.opencompute.org/documents/grand-teton-intel-based-cpu-tray-specification-v1-0-pdf →Settled management SoC. Reuse.
https://www.aspeedtech.com/server_ast2600/ →Standard NIC form factor. Reuse.
https://www.opencompute.org/documents/grand-teton-intel-based-cpu-tray-specification-v1-0-pdf →Standard NVMe. Reuse.
https://www.opencompute.org/documents/grand-teton-intel-based-cpu-tray-specification-v1-0-pdf →Standard rack power. Reuse.
https://engineering.fb.com/2022/10/18/open-source/ocp-summit-2022-grand-teton/ →The slice openWafer designs
In an AI node the host is all reuse — CPU, DRAM, NIC, BMC, power; OCP standardised every bit of it. The value and the energy concentrate in two places: the accelerator silicon and the wires between accelerators. openWafer’s slice is both — the compute die, and co-packaged optical I/O so bits move between chips in light instead of copper, where a moved bit costs the fewest joules. That optical interconnect is the photonic tile from the frontier build, dropped into the rack. The datacenter is where the wrist and the frontier meet the same law: design where the joules are.